Updating computer clock via internet

Dynamic reconfiguration is the ability to dynamically modify the transceiver channels and PLL settings during device operation.

To support dynamic reconfiguration, your design must include an Avalon master that can access the dynamic reconfiguration registers using the Avalon-MM interface.

f PLLs support both integer frequency synthesis and fine resolution fractional frequency synthesis.

A link is defined as a single entity communication port. A transceiver channel is synonymous with a transceiver lane.

For example, a 10GBASE-R link has one transceiver channel or lane with a data rate of 10.3125 Gbps. Each transceiver channel operates at a lane data rate of 10.3125 Gbps.

Transceiver banks with six transceiver channels have two master CGBs.

Master CGB1 is located at the top of the transceiver bank and master CGB0 is located at the bottom of the transceiver bank.

It can operate over the full range of supported data rates required for high data rate applications.

A fractional PLL (f PLL) is an alternate transmit PLL that generates clock frequencies for up to 12.5 Gbps data rate applications.The master CGB divides and distributes bonded clocks to a bonded channel group.It also distributes non-bonded clocks to non-bonded channels across the x6/x N clock network. The local CGB is used for dividing and distributing non-bonded clocks to its own PCS and PMA blocks.A PMA is the transceiver's electrical interface to the physical medium.The transceiver PMA consists of standard blocks such as: The PCS can be bypassed with a PCS Direct configuration.The Avalon-MM master enables PLL and channel reconfiguration.